In microelectronic devices, miniaturization of elements and high integration has progressed in order to improve their performance with decreasing size. Disadvantageously in semiconductor devices, miniaturization techniques are approaching their limits. While devices having a three-dimensional structure such as wire bonding, flip chips, bumps or the like are being increasingly used, higher integration is still desired.
A technique for forming an electrode by forming a fine via that penetrates silicon, and filling the via with a conductive material such as copper (TSV technique) has been developed. Usually, in the case where copper is used as the electrode in the TSV technique, an opening is provided in a silicon substrate (1), and then a silicon oxide layer (2) (i.e., a low-k dielectric layer) and a barrier metal layer (3) of titanium, tantalum or the like are formed on an inner wall of the opening. Subsequently, a copper seed layer (4) is formed by a metal organic chemical vapor deposition method or a physical vapor deposition method (FIG. 1). Next, a protective film is formed with a resist resin (5) on the copper seed layer other than the portion on which the electrode is formed (FIG. 2). A metal such as copper (6) is embedded into the portion in which the protective film is not formed to form a bump. Disadvantageously, connection reliability is reduced by a surface oxidation phenomenon if the copper is not protected. Accordingly, usually, a nickel layer (7) and a solder layer of gold or an alloy of tin and silver (8) are each laminated (FIG. 3). Then, the bump (9) is formed by removing the resist resin (FIG. 4).
The copper seed layer and the barrier metal layer are formed not only within the opening of the silicon substrate but also on the surface of the silicon substrate, and remain even after the resist is removed. For this reason, the remaining copper seed layer and barrier metal layer must be removed by an etching solution (FIGS. 5 and 6). Among them, as a method for wet etching the copper seed layer, methods using an etching solution composed of an acid and an oxidizer, i.e., a mixed solution of sulfuric acid and hydrogen peroxide are widely used (Japanese Patent Application Laid-Open Nos. 2000-286531 and 2009-120870). Methods using an etching solution containing cupric chloride or ferric chloride are also widely known (Japanese Patent Application Laid-Open No. 2008-285720). Disadvantageously, these etching methods not only etch the copper seed layer formed in the electronic substrate, but also the bump is deformed because nickel used to form the bump is also etched.
Accordingly, the need remains in the art for a solution that can selectively etch copper or copper alloy relative to nickel-containing material from a microelectronic device simultaneously including copper or copper alloy and nickel-containing material.